The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to interconnect structures and methods of fabricating an interconnect structure.
A back-end-of-line (BEOL) interconnect structure may be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing with each other and with the environment external to the chip. A method of forming a BEOL interconnect structure is a damascene process in which via openings and trenches etched in one or more dielectric layers are filled with metal to create multi-level, high density metal interconnections. For example, in a dual-damascene process, the trenches and via openings are filled with metal using a single blanket deposition followed by planarization. The damascene processes used in forming BEOL interconnect structures face challenges as the dimensions of devices and associated interconnects shrink. One of these challenges is the inability to accurately overlay the different patterns for the trenches and via openings.
Improved interconnect structures and methods of fabricating an interconnect structure are needed.